Static random access memory (SRAM) is often implemented with many SRAM cells connected to shared bitlines. For example, in a programmable logic device (PLD) such as a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a field programmable system on a chip (FPSC), or other type of programmable device, bitlines may connect many hundreds of SRAM cells distributed throughout the PLD. Such SRAM cells may be used, for example, to configure the PLD for operation.
SRAM implementations typically rely on asynchronous sense amplifiers which operate in a constant state of detection. As SRAM cells are read, differential signals on the bitlines are detected by the sense amplifiers and interpreted as data values. However, conventional sense amplifier implementations may be susceptible to error. For example, conventional sense amplifiers may detect and interpret incorrect data values in cases where the differential signals initially develop in the wrong direction, or where the differential signals are too small. Moreover, power may be wasted in such implementations where sense amplifiers are maintained in a constant state of detection and receive a current source routed to all sense amplifiers of a memory.
Accordingly, there is a need for an improved approach to the operation of sense amplifiers that increases accuracy and reduces the amount of wasted power associated with conventional implementations.